When it is desired to minimize the energy consumption of a synchronous digital electronic circuit for which timing is provided by a clock signal, while maintaining its performance, it is known to apply to that circuit a clock frequency adapted to a given supply voltage. By “synchronous circuit” is meant a “circuit for which timing is provided by a clock”.
It has moreover been proposed to adapt the clock frequency according to the performance desired for the system, and also to modify the supply voltage, a technique known under the acronym DVFS (for “Dynamic Voltage and Frequency Scaling”).
These techniques are applied in particular in the case of GALS architectures (GALS standing for “Globally asynchronous Locally Synchronous”), in which the system concerned is divided into different VFIs (VFI standing for “Voltage Frequency Island”). Such architectures are for example produced in the form of SoCs (SoC standing for “System on Chip”).
The variable supply voltage to apply to an electronic circuit is generated by a module named “voltage actuator”, for example in accordance with the technique referred to as “Vdd-hopping”, described in the paper “A power supply selector for energy- and area-efficient local dynamic voltage scaling”, by S. Miermont, P. Vivet and M. Renaudin, in Lecture Notes in Computer Science, Volume 4644, pages 556-565, 2007.
As regards the clock signal of variable frequency to apply to the electronic circuit, this is generated by a module referred to as “frequency actuator”; such a frequency actuator is for example produced in the form of an FLL (for “Frequency Locked-Loop”) or in the form of a PLL (for “Phase Locked-Loop”).
Such frequency actuators are produced in the form of a system operating in a closed loop which includes in particular a controller influencing the variable generated according to the measured error (difference between the variable measured and the setting) and according to a control law.